1. Field of the Invention
The present invention relates to a mixed technology integrated circuit wherein high density CMOS structures and lateral bipolar transistors having high Early voltage and electrical efficiency are integrated.
2. Description of the prior art
Mixed technology integrated circuits are finding growing opportunities of utilization because of their exceptional versatility. On the other hand the request for an ever increasing density of these integrated devices in order to increase miniaturization of the systems emphasizes compatibility problems in forming different technology structures such as bipolar transistors and MOS (CMOS) transistors monolithically integrated in the same chip.
In particular, the realization of high density, mixed technology integrated circuits necessarily implies, according to the most modern fabrication processes, a drastic reduction of the junction depth of diffusions. This fact, while bringing important advantages in making effective CMOS structures, tends to penalize electrical efficiency and Early voltage characteristics of lateral bipolar transistors. In fact in first-generation, mixed technology integrated circuits wherein the isolation field oxide was geometrically defined after its formation and wherein the junction depth remained relatively large (e.g. from 3 to 4 pm for p.sup.+ diffusions), the efficiency of lateral bipolar transistors remained satisfactory, but the structures could not be made very dense. Vice versa in mixed technology integrated circuits made in accordance with the most modern techniques, which contemplate the growth of the isolation field oxide on areas pre-defined by means of a silicon nitride mask and the formation in a self-alignment mode of superficially enriched well regions, a high density of the integrated structures may be obtained, though accompanied by a consistent drop of electrical efficiency of lateral bipolar transistors because of a dramatically increased loss of collector current toward the isolation junctions (and the substrate) which surround the transistor region.
This mechanism is schematically depicted in FIGS. 1 and 2, wherein a partial schematic cross section of a first generation, mixed technology integrated device and of a similar integrated device made in accordance with the most modern techniques are respectively depicted. Symbols and polarities of the different regions and diffusions are customary and immediately comprehended by a skilled technician without requiring a redundant detailed description thereof.
As indicatively shown by the arrows departing from the emitter junction of the bipolar transistor (PNP in the shown example) and which identify the current lines, in the case of the low density of integration device of FIG. 1, the major portion of the emitter current is effectively gathered by the transistor's collector. On the contrary in a high density integrated device made according to modern techniques, as depicted in FIG. 2 disregarding the accuracy of a scale representation between the two figures, wherein the collector junction depth is typically only 0.7 .mu.m, a consistent portion of the emitter current is lost to ground through the p-silicon substrate of the integrated device, being gathered by the p-type isolation junction of the transistor.
In this kind of devices, the ratio between the collector current and the current lost through the isolation junction: Ic/Isubstrate, is evaluated to be about 8, while the Early voltage presented by the lateral PNP transistor is only about 20 V.
This drop of electrical efficiency of lateral bipolar transistors cannot be avoided because in order to increase the integration density especially of CMOS structures it is necessary to reduce the lithographic dimensions, the junction depths and to employ a field oxide formed so as to permit the formation in a self-alignment mode of the superficial enrichment regions of the well (p-well in the case shown in FIG. 2) which are necessary for preventing undesired superficial inversions (creation of parasitic MOS transistors) and these restraints determine the above discussed problem in lateral bipolar transistors. In fact for countering the loss of current toward the substrate, the collector is made as close as possible to the emitter causing in turn a low Early voltage.